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IP200
Interpolation Circuit for Incremental Measuring Systems
Data Sheet
GEMAC
Gesellschaft fur Mikroe lektronikanwendung Chemnitz mbH
Zwickauer Strae 227 D-09116 Chemnitz, Germany
+49 371 33 77 - 0 +49 371 33 77 272 www.gemac-chemnitz.de interpolation@gemac-chemnitz.de sales@gemac-chemnitz.de Date: 20.04.04 Page 1 of 30 Phone: Fax:: Internet: Email:
Title:
Data Sheet GC-IP200
Name of Document:
43500-DB-2-1-E-IP200.pdf
Contents
1 2
OVERVIEW ..................................................................................................................................... 3 INPUT SIGNALS.............................................................................................................................. 5 2.1 2.2 2.3 ANALOGUE SIGNAL PROPERTIES .................................................................................................... 5 SIGNAL CORRECTION ................................................................................................................... 5 REFERENCE SIGNALS / INDEX POINT............................................................................................... 6
3
A/D-CONVERTER ........................................................................................................................... 7 3.1 INPUT CIRCUIT RATING ................................................................................................................. 7
4
DIGITAL OPERATION MODES ........................................................................................................ 8 4.1 4.2 4.3 4.4 4.5 OUTPUT SIGNALS / COUNTER VALUE .............................................................................................. 8 ERROR SIGNAL............................................................................................................................ 9 INTERPOLATION RATE................................................................................................................... 9 INTERVAL TIME / MAXIMUM INPUT FREQUENCY ................................................................................. 9 GLITCH FILTER .......................................................................................................................... 10
5
INTERFACES ................................................................................................................................ 11 5.1 STRUCTURE.............................................................................................................................. 11 5.2 SERIAL INTERFACE (SPI) ............................................................................................................ 11 5.2.1 Signals............................................................................................................................. 11 5.2.2 Protocol............................................................................................................................ 12 5.2.3 Synchronous / Asynchronous Mode ................................................................................... 13 5.3 PARALLEL DATA PORT................................................................................................................ 14
6
REGISTERS .................................................................................................................................. 15 6.1 6.2 6.3 6.4 READ REGISTERS ...................................................................................................................... 15 WRITE REGISTERS ..................................................................................................................... 15 COMMANDS .............................................................................................................................. 15 CODING ................................................................................................................................... 16
7 8 9
MEASUREMENT TRIGGER ........................................................................................................... 20 ERROR PROCESSING .................................................................................................................. 21 RESET / CONFIGURATION ........................................................................................................... 22 9.1 9.2 9.3 RESET PROCESSING .................................................................................................................. 22 CONFIGURATION........................................................................................................................ 22 CONFIGURATION BITS DEFAULTS ................................................................................................. 23 SIGNAL PROPAGATION TIME................................................................................................... 23 ELECTRICAL CHARACTERISTICS ............................................................................................ 24 MECHANICAL CHARACTERISTICS........................................................................................... 26 PINOUT .................................................................................................................................... 26 DOUBLE FUNCTION PINS ............................................................................................................. 27 PACKAGING .............................................................................................................................. 27 BOND PATTERN......................................................................................................................... 28 REVISION HISTORY .................................................................................................................. 30
10 11 12 12.1 12.2 12.3 12.4 13
GEMAC
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Zwickauer Strae 227 D-09116 Chemnitz, Germany
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Title:
Data Sheet GC-IP200
Name of Document:
43500-DB-2-1-E-IP200.pdf
1
Overview
The IP200 interpolation circuit is designed for connection to incremental position and angle measuring systems with sine-shaped output signals with a 90 phase shift. It can be operated at a large number of transducer systems working according to the most varied measuring principles. With a maximum interpolation rate of 200 the IC is capable to split the input signal period into up to 200 segments. A counter value can be output via parallel or serial interface, respectively. Different interfaces and flexible configuration types enable the use of the IP200 in single-chip interpolation systems, in microcontroller-based measuring devices and in multi-channel systems alike. Proprietary automatic gain and offset control, as well as the possibility of a analogue phase correction ensure a high measuring precision under industrial conditions. The integrated two-level measuring value trigger and the additional parallel high speed output makes the IC suitable for use in real time applications.
Block Diagram
Reset Clock Interpolation Rate Interval Time Filter ... Config Cosine Error ? Inst-Amp ADC Sine ADC Controller PHI A/B RS422 Counter parallel IF
Phase
Trigger
serial IF
ATAN
Filter
Inst-Amp Reference Comp
Analog
Digital
GEMAC IP200
Figure 1 Inst-Amp ADC ATAN A/B serial IF parallel IF Instrumentation amplifier Analogue-Digital-Converter ARCTAN-processing-unit Generation of the A/B-signals Serial Interface Parallel Interface
GEMAC
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Title:
Data Sheet GC-IP200
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43500-DB-2-1-E-IP200.pdf
Features
Analogue Input Package 3 channels: sine/cosine/reference signal Standard connection 1V pp (differential) Input frequency of up to 400kHz up to 1.25MS/s Single-Ended Input 2.4Vpp Automatic gain and offset controller External potentiometer for analogue phase correction 200, 160, 100, 80, 50, 40, 25, 20 28 - Bit counter 90 - square wave sequences Error signal Via configuration pins Via serial interface (SPI) For Configuration and measuring value output 16-Bit synchronous/asynchronous mode Not required for low-cost minimal applications For measuring value output 16-Bit wide Up to 40MBit/s bandwidth Filter for suppressing edge noise at low speed input signals Programmable interval time for adapting the circuit to low speed digital components Two-level edge-controlled measuring trigger Programmable sensor error response TQFP64 (10mm x 10mm x 1mm) or DIE
AD converter
Signal correction
Interpolation rates Measuring result outputs
Configuration options
Serial interface (SPI)
Parallel output
Miscellaneous
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Title:
Data Sheet GC-IP200
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43500-DB-2-1-E-IP200.pdf
2
Input Signals
The two input signals for the interpolation function are analogue voltages (sine/cosine) with a sine-shaped dependency on the measured value (position or angle respectively) with a phase shift of 90 between these two analogue voltages, related to one period of the scale. A third input signal serves as a reference signal for determining the zero or reference point of the scale. All the three input signals are processed as differential signals.
2.1
Analogue Signal Properties
Difference Signal Sin = SinP-SinN
Angle 0 Vdiff Peak to Peak
SinP SinN
90 Phase Shift Vdiff Peak to Peak
CosP CosN Difference Signal Cos = CosP-CosN
Figure 2 Differential Analogue Input Voltage1) Analogue Input Voltage VDiff (nominal) Input Range for VDiff Maximum Signal Offset Error Sine/Cosine Phase Shift 1) on pins SINP, SINN, COSP, COSN 500mV pp 1Vpp 0.8Vpp ... 1.2Vpp 100mV 90 (adjustable 10)
2.2
Signal Correction
The input signals are subject to a automatic gain and offset control patented by GEMAC. The amplitude controller is specified for a control range of 20% of nominal input voltage. The offset of the external signals must not exceed a value of 10% of nominal input voltage. The phase shift of the input signals can be statically adjusted by a external analogue potentiometer in a range of 10 (also refer to Application Notes 4300x-AN-3-0-E-IPx.pdf). A Chip Reset results in setting the gain-offset-controller to midscale. For achieving the best interpolation performance, the gain-offset-controller needs approximately 20 signal periods for reaching a steady state. Until this time, the input signal frequency must not exceed 50% of the specified maximum signal frequency (refer to chapter 4.4). All signal errors figures as a union in the IP200. In some special cases means decreasing of one signal error result in a wider permissible range of another signal error. For achieving the highest performance of the automatic gain-offset-controller, it is recommended to carefully adjust the phase shift on the connected sensor itself. This is important especially for high interpolation rates.
GEMAC
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Title:
Data Sheet GC-IP200
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43500-DB-2-1-E-IP200.pdf
2.3
Reference Signals / Index Point
A third output of the measuring system - typically called reference, index point or zero point signal considered to be activated, if the difference of the signals at the REFP and REFN pins becomes greater than the positive hysteresis voltage V RPH and is considered to be deactivated if this voltage becomes smaller than the negative hysteresis voltage VRPL.
REFN REFP respectively: VRPH VRPL 0V
VRP = REFP - REFN
inactive
active
inactive
Figure 3 VRPL (typical) VRPH (typical) Hysteresis (typical) = -6mV = +6mV = 12mV
If a sensor without reference signals is used, defined levels on pins REFP and REFN are necessary to setting the index point always active or always inactive, respectively.
GEMAC
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Title:
Data Sheet GC-IP200
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43500-DB-2-1-E-IP200.pdf
3
A/D-Converter
The IP200 contains two integrated Analogue Digital Converter with a maximum sample rate of 1.25MS/s. In some special applications, were the analogue sensor signal do not match the analogue front end (AFE) specification (nominal 1V pp), it is possible to connect the input signals to the Analogue Digital Converter inputs, bypassing the AFE. In this case, the conditioned sensor signals must be sine shaped with a amplitude of 2.4V pp centred around the ADC common mode level V0. The IP200 includes a on-chip reference voltage circuit that generates the V0 with a nominal voltage of 2.375V.
3.1
Input Circuit Rating
VMAX = V0 + (VRP - VRN) Reserve for Gain- and Offset Errors Operating Range VNOM = 1.3 (VRP - VRN) (Nominal Amplitude Peak-Peak) V0 = 1/2 (VRP + VRN) (Midscale Voltage)
Reserve for Gain- and Offset Errors VMIN = V0 - (VRP - VRN)
VRP : positive ADC-Reference Voltage VRN : negative ADC-Reference Voltage
Figure 4 The following reference voltage levels appear on external pins: Pin RSH RCH RSL RCL V0 UNOM UMAX UMIN Nominal Value 3.30V 3.30V 1.45V 1.45V 2.375V 2.405V 4.225V 0.525V
Positive Reference Voltage (VRP) Sine-ADC Positive Reference Voltage (VRP) Cosine-ADC Negative Reference Voltage (VRN) Sine-ADC Negative Reference Voltage (VRN) Cosine-ADC Midscale Voltage for external analogue circuitry Nominal amplitude Maximum voltage Minimum voltage
For information about the tolerances see chapter Electrical Characteristics.
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Data Sheet GC-IP200
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4
4.1
Digital Operation Modes
Output Signals / Counter Value
The position/angle result is available via the integrated serial interface in a 28-bit two's-complement format. As described, the zero point can be generated using the REFP and REFN reference signal inputs, or it can be set via the serial interface. By activating the trigger input, measuring result can be kept in a 2-level deep buffer register in a manner asynchronous to the access via the interfaces. Simultaneously, the IP200 outputs the phase shifted square wave sequences (known by incremental measuring transducers) which can be counted in single or quadruple way. A synchronous reference pulse is generated when the angle of 0 (refer also to Fig. 2) is passed through and when the analogue differential input voltage between REFP and REFN exceed the positive comparator hysteresis level. If the differential input voltage is permanently above this level, the reference pulse is generated once during every signal period. A configuration bit can disable the generation of the reference pulse.
A B OREF internal -5 Counter -4 tpp tpp: minimal Interval Time / Edge Interval -3 -2 -1 0 1 2 1 0 -1 -2 -3 -4 -5
Figure 5
Note that the IP200 IC based on a digital interpolation method. This means that the quantization errors (the so-called 1 errors) which are inevitable with A/D converters are superposed upon the speed-proportional A/B output signals. Analogue control systems must feature a corresponding low-pass behaviour when the IC is used in such systems.
GEMAC
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Zwickauer Strae 227 D-09116 Chemnitz, Germany
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Title:
Data Sheet GC-IP200
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43500-DB-2-1-E-IP200.pdf
4.2
Error Signal
An error signal is generated if the input signals are no longer plausible. The error signal is also generated if the input frequency is so high that the square-wave signals are unable to follow, and/or when the maximum input frequency is exceeded. The evaluation of the internal error sources is activated via an error mask register. The response of the square-wave outputs in the event of an error can also be configured via this register. The NERR and NRES pins can be connected in order to start a re-synchronisation process of the IC in the event of an error.
If the error signal was activated, and/or if one of the error bits was set in the result register, the present measuring result and all the following results must be discarded. Following elimination of the cause of the error and a reset of the error bit, the reference point must once again be passed by for absolute value measurements!
4.3
Interpolation Rate
The interpolation rate can be set at 200, 160, 100, 80, 50, 40, 25 and 20. The interpolation rate as defined for the purposes of this application is the number of increments into which one sine period of the input signal is divided. This also corresponds to the number of edge changes on the A/B output signals per input signal period. This means that the number of square-wave periods at the A and B outputs totals 1/4 of the interpolation rate per input signal period.
In the event that a standard interpolation counter or quadrature decoder is connected to the A/B outputs, this must work in "quadruple evaluation" mode in order to achieve the full interpolation rate.
4.4
Interval Time / Maximum Input Frequency
The interval time (IT) and the minimum edge distance tpp at the output signals, respectively, can be set in binary steps at values between 1/fosz and 128/fosz. In counter mode (the SPEED Bit in the CFG0 Register being set), the maximum input frequency totals fmax=fosc /96. In all the other modes, the maximum input frequency is limited by the minimum pulse distance at the output, where: fmax fosc: IR: IT: 0.9*fOSZ /(IRIT) < fosz/96 Clock frequency at Pin XA Activated Interpolation Rate Activated Interval Time
The limit values are a maximum input frequency of aprox. 400kHz with a clock frequency of 40MHz on the one hand, as well as a guaranteed edge distance of 128s at the A/B signals with a clock frequency of 1MHz on the other. Between these two limits, a large number of specific systems can be adapted by selecting a suitable clock frequency and interval time of the IP200.
These values apply on condition of an adjusted phase between the input signals and a steady state of the internal gain-offset-controller. Until this time, the input frequency must not exceed 50% of the specified maximum frequency.
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Data Sheet GC-IP200
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Clock Frequency Examples
fOSC = 40MHz tpp fmax 1 31ns 225k 2 62ns 113k 4 125ns 56k 8 250ns 28k 16 500ns 14k 32 1s 7k 64 2s 3.5k 128 4s 1.8k 1 31ns 400k 2 62ns 400k 4 125ns 225k 8 250ns 113k 16 500ns 56k 32 1s 28k 64 2s 14k 128 4s 7k fmaxCNT = 400kHz IR IT tpp 1 31ns 2 62ns 4 125ns 100 8 250ns 16 500ns 32 1s 64 2s 128 4s 1 31ns 2 62ns 4 125ns 25 8 250ns 16 500ns 32 1s 64 2s 128 4s
IR
IT 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128
200
50
tpp 31ns 62ns 125ns 250ns 500ns 1s 2s 4s 31ns 62ns 125ns 250ns 500ns 1s 2s 4s
fmax 180k 90k 45k 22.5k 11.3k 5.6k 2.8k 1.4k 400k 360k 180k 90k 45k 22.5k 11.3k 5.6k
IR
IT
160
40
fmax 360k 180k 90k 45k 22.5k 11.3k 5.6k 2.8k 400k 400k 360k 180k 90k 45k 22.5k 11.3k
IR
IT 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128
80
20
tpp 31ns 62ns 125ns 250ns 500ns 1s 2s 4s 31ns 62ns 125ns 250ns 500ns 1s 2s 4s
fmax 400k 225k 113k 56k 28k 14k 7k 3.5k 400k 400k 400k 225k 113k 56k 28k 14k
marked cells: normal cells:
Error FAST1 appears on speed overflow Error FAST2 appears on speed overflow
4.5
Glitch Filter
In order to avoid permanent toggling of the downstream counters as a result of analogue noise of the input signals while the measuring system is in standstill, a digital filter can be optionally activated for the squarewave outputs (pin / bit GFE). In such a case, the minimum edge distance at the output (t pp) is then automatically set at 2048 / fosc while the measuring system is in standstill or at smaller input frequencies.
Note that in the switching range to the automatic activation / deactivation of this filter, the A/B output signals are not speed-proportional in each case!
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Title:
Data Sheet GC-IP200
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43500-DB-2-1-E-IP200.pdf
5
Interfaces
The measurement results can be read out over the integrated serial interface (SPI). It is also possible to make a more detailed configuration of the IP200 IC over this interface than over hardware. For high speed applications the additional 16-bit wide parallel port allow to read out the measurement results continuously with up to 32MBit/s.
5.1
Structure
WR-Register Bank
W0 8 Bit W1 W2
SPI SPI
W3
D_IN D_OUT ADR RD0/ST
W4
SPI-RD-Reg.
D Q
RD-Register Bank
R0 CE 32 Bit R1 ... ...
PAR-RD-Reg.
D Q H
Cycle Counter C-CNT SYNC
R8
D(15:0) OUTHIGH
L CE nDTHLD 1
Figure 6
5.2
Serial Interface (SPI)
The serial interface contains a 16-bit shift register for read accesses and write accesses each. An additional 16-bit hold register series for the intermediate storage of the two MSB's during read accesses. An 8-bit address register is used for both read and write accesses. Writing into the IP200 takes place in a byteoriented manner whilst reading being a word-oriented process. Transmission itself is effected as 16-bit words. A read command triggers the pertinent data output during the next access. A single-byte command is executed at the end of data transmission. Up to 16 channels can be operated at this interface. The hardware address of the IC is determined by reading the DP(3:0) pins by a special command. 5.2.1 Signals
The IP200 is a slave which evaluates commands and data received, but which is unable to start a communication process. The SPI protocol is executed via 4 lines: SDI SDO SCLK SEN Data input Data output (open drain), SDO also serving as the RDY signal Clock Enable
The used SPI-protocol is not compatible to the usual micro controller- or DSP-families.
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Each transfer process is triggered by the sending of a command. To this effect, SEN is kept low during 16 SCLK clock cycles. The input data at SDI is evaluated a the rising edge of SCLK. At the same time, the shifting of the data of the hold register is triggered at every rising edge at SCLK.
SPI-Access:
tw tH tL Start command processing
SCLK
tVDI tVDO tSETDI tRDY i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 XX
SEN
tRDY
SDI SDO
XX
RDY
o15
o14
o13
o12
o11
o10
o9
o8
o7
o6
o5
o4
o3
o2
o1
o0
RDY
Load bit 15 from SDI
Send bit 14 to SDO
Figure 7 Name
tH tL tw tRDY tVDI tSETDI tVDO 2x 2x 1x 3x
Min
TOSZ + 15 TOSZ + 15 TOSZ + 15 TOSZ + 15 ns1) ns1) ns1) ns
Max
Description
SPI clock, H time SPI clock, L time Waiting time between SEN falling and SCLK rising Switching delay RDY / SDO from SEN Time between SCLK rising and data read Setup time SDI before SCLK Time between SCLK rising and data output
4 x TOSZ + 15 ns 15 ns 5 TOSZ + 15 ns
1 x TOSZ + 15 ns1) 4 TOSZ + 15 ns
5.2.2
Protocol
Name 11 X
H32) H32) H3
2)
Bit No. at signal SDI 15 14 13 12 0 X 0 0 nB2) 0 0 1 nB2) 1 0 0 nB2) 1 0 1 nB2) 0 1 0 nB2) 0 1 1 nB2) 1 1 X
1) 2)
Description Reserved Write Address Write Data Write Command Read Byte 0 + 1 (LSB) 1) Read Byte 2 + 3 (MSB) Output Read-Register
10 X
H22) H22) H2
2)
9 X
H12) H12) H1
2)
8 X
H02) H02) H02) H02) H02) H02)
H32) H32) H32)
H22) H22) H22)
H12) H12) H12)
7 X A7 D7 C7 A7 X X
6 X A6 D6 C6 A6 X X
5 X A5 D5 C5 A5 X X
4 X A4 D4 C4 A4 X X
3 X A3 D3 C3 A3 X X
2 X A2 D2 C2 A2 X X
1 X A1 D1 C1 A1 X X
0 X A0 D0 C0 A0 X X
RES WRA WRD WRC RD0/ST RD1 NOP
command load the internal data into a 32-bit hold register bit must be set to zero in single-channel systems
Bit nB H(3:0) A(7:0) C(7:0) D(7:0)
Name Broadcast mode (Low-active) Hardware address Register address Command Data word
Description 0: Command to all channels (for WRA/WRD/WRC only) 1: Command to the channel addressed by H(3:0) IP200-Channel address for single access (nB=1) Default: 0x00 IP200-Register address Single-word command Write data (readed data appears at SDO)
Command word examples Set address register in all channels connected at 0x01: Write data 0x48 in channel 0x04: Read L word from register 0x07, one IC existing only: Configuration of the hardware address in all the channels connected:
0x1001 0x6448 0x8007 0x3000 Title:
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5.2.3
Synchronous / Asynchronous Mode
Read data is loaded into the hold register by the RD0/ST command. This takes place when the internal sequential control counter and the SYNC register have the same contents (synchronous mode) or when the ASYNC bit is set (asynchronous mode). Pin SDO is low during the waiting time (meaning of RDY) . With the SPI working in synchronous mode, the output data can be assigned to a sample time. Equidistant measurement is possible (refer also to the application example). Higher transmission rates are achieved in asynchronous mode.
Example: 32-bit read access synchronous with internal cycle counter
SEN *) any command RD0 / ST RD1 RD0 / ST *)
SDI
SDO Hold register
XXXXXX
SYNC
RDY
Byte 0 +1
RDY
Byte 2 + 3
SYNC
RDY
Data to be transmitted
Figure 8
Example: 16-bit read access, asynchronous, 3 channels
SEN
SDI
RD0 H0
RD0 H1
RD0 H2
RD0 H0
SDO
XXX
Data H0
Data H1 Data to be transmitted Data to be transmitted
Data H2
Hold register channel 0 Hold register channel 1 Hold register channel 2
Data to be transmitted
Figure 9
Example: write access 1 Channel
SEN
Example: command execution 1 channel
SEN Execution of command
SDI
WRA (address)
WRD (data)
SDI
WRC (Command) XXX
SDO
XXX
XXX
SDO
Figure 10
Figure 11
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Data Sheet GC-IP200
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5.3
Parallel Data Port
This interface outputs the last activated SPI read register synchronized to the IP200 internal sequential control counter. The appearing data are separated into two 16-bit words. After reset, the data of the SPI read register address 0x00(MVAL)appears on DATA(15:0) by default.
Sequential Control Counter DATA(15:0) OUTHIGH STRB
29
30 D(31:16)
31
0
1 D(15:0)
13
14
15
16
17 D(31:16)
XA Signal T Delay TDelay < 15ns
Figure 12 To reduce switching noise on the data port the Data outputs DATA(15:8) will be switched 1 clock cycle after the outputs DATA(7:0). That's why the value at DATA(15:8) is undefined in the clock cycles 0 and 16. For external components the edges of OUTHIGH can be used to register the new valid data. The level on OUTHIGH show, which part of the 32-bit read value is active on the data pins (either LSB or MSB). A optional Strobe-Signal (on pin OREF) can be activated via TSTRB bit in the configuration register TSTCFG.
To get out a desired read register on parallel port, it is necessary to read this register via serial interface first. EVERY other SPI access at any time can change the behaviour of parallel port. If the parallel interface be used solely as output port, please select carefully the corresponding attachment circuit of the configuration and the double function pins at the IP200. Please refer also application notes in the document 4300x-AN-3-0-E-IPx.pdf.
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Data Sheet GC-IP200
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6
Registers
The IP200 contains 16-bit and 32-bit read registers, as well as 8-bit write registers. The addresses are assigned separately for the read and write registers. A third address space is reserved for commands.
6.1
Read Registers Description Measurement Value / Status Configuration / Status Interpolation results Controller Sine Controller Cosine Counter Value / Status Byte 3 Byte 2 Byte 1 MVAL ERRMASK DPHI SOFF COFF CNT CFG1 CFG0 PHI SGAIN CGAIN STAT Byte 0
Address 0x00 0x01 0x03 0x04 0x05 0x07
6.2
Write Registers Description Configuration Configuration Configuration SPI-Synchronisation Configuration IC-Test Controller Sinus (Gain) Controller Sinus (Offset) Controller Cosine (Gain) Controller Cosine (Offset) Name CFG0 CFG1 ERRMASK SYNC TSTCFG SGAIN SOFF CGAIN COFF
Address 0x00 0x01 0x02 0x03 0x04 0x07 0x08 0x09 0x0A
6.3
Commands Name Channel Description The hardware address will be read from pins DP(3:0). Send this command always as broadcast command! In multi-channel systems this command must send and executed first after a global reset! The parallel counter (register CNT) is reset, the error register is reset. Note, that the values of trigger hold registers remains unchanged. The gain-offset-controller will be set to midscale.
Command 0x00
0x01 0x02
Reset Counter Reset Controller
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6.4 MVAL
Coding Measurement Value / Status 0x00 0x00
31:4 CNT 3 FAST1 2 SENSERR 1 TRGOVL 0 FROZEN
Read Address Default
CNT FAST1 SENSERR TRGOVL FROZEN
Counter Value or Trigger Value respectively (28-bit - two's complement) Speed Error Sensor Error (ADC overflow, sensor breakage, gain- or offset error) Trigger Overflow 0 CNT contains the current counter value 1 CNT contains the oldest trigger value stored
For more detailed information about the functions of these bits refer to chapter 7 and 8. Examples:
0x00004200 0x00004201 0x00004203 0x00004204 0x00004205 Result 0x00000420 is current counter value Result 0x00000420 is trigger value, no errors Result 0x00000420 is trigger value, one or more trigger events are lost Sensor error, Result invalid Sensor error, Result invalid
CNT Read Address Default
Counter Value / Status 0x07 0x00
31:4 CNT 3 GCOMP 2 OCOMP 1 AMPERR 0 FAST1
CNT FAST1 AMPERR OCOMP GCOMP
Counter Value (28-bit - two's complement) Speed Error Sensor Error (ADC overflow or sensor breakage) Offset Error Gain Error
For more detailed information about the functions of these bits refer to chapter 7 and 8.
STAT Read Address Default
7:6 TR(1:0)
Status 0x01 (Byte 0) 0x00
5 Fast2 4 Fast1 3 ADCOVL 2 BQLO 1 OCOMP 0 GCOMP
GCOMP OCOMP BQLOW ADCOVL FAST1 FAST2 TR(1:0)
Gain Error Offset Error Sensor Breakage ADC Overflow Speed Error (Counter and A/B-Signals) Speed Error (A/B-Signals) Status of Trigger-Hold-Registers
For more detailed information about the functions of these bits refer to chapter 7 and 8.
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PHI Read Address
Interpolation Result - Phase Angle 0x03 (Byte 1/0)
15:8 0x00 7:0 PHI
PHI
Interpolated Phase Angle of Input Signals (unsigned, binary) Scaling: 0 ... 200 = 0... 360, if IR(2) = 1 0 ... 160 = 0... 360, if IR(2) = 0 Interpolation Result - Phase Angle Difference 0x03 (Byte 3/2)
15:8 0x00 7:0 DPHI
DPHI Read Address
DPHI
Difference to last Phase Angle (two's complement) Scaling: -100 ... +100 = -180... +180, if IR(2) = 1 -80 ... +80 = -180... +180, if IR(2) = 0
CFG0 Read Address Write Address Default
7 SPEED
Configuration Register 0 0x01 (Byte 1) 0x00 Configuration pins will be read (IT0=0)
5:3 IT(2:0) 2:0 IR(2:0)
6 GFE
IR(2:0) 000 001 010 011 100 101 110 111
Interpolation Rate 160 80 40 20 200 100 50 25
Square Wave Periods A/B 40 20 10 5 50 25 121/2 61/4
IT(2:0) 000 001 *) 010 011 *) 100 101 *) 110 111 *)
*)
Interval Time tpp in 1/ fOSZ 1 2 4 8 16 32 64 128
only selectable over SPI
GFE
0 1
Glitch Filter deactivated Glitch Filter activated
SPEED
0 1
Configure speed monitoring for A/B outputs Configure speed monitoring for internal counter
The double function pins SDI and TRG are used for initializing of the GFE and SPEED bits during reset processing. The IT0 bit can only be assigned over serial interface. For more information refere also to IP200 application notes.
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CFG1 Read Address Write Address Default
Configuration Register 1 0x01 (Byte 2) 0x01 0x00
*)
7:3 2 1 0 00000*) DISREG DISREF TRSLP Bits must remain unchanged in order to guarantee the correct functioning of the IC
DISREG
0 1 0 1 0 1
Internal automatic gain-offset-controller activated Internal automatic gain-offset-controller deactivated Trigger event occurs on the falling edge of pin TRG Trigger event occurs on the rising edge of pin TRG Reference point processing activated Reference point processing deactivated
TRSLP
DISREF
ERRMASK Read Address Write Address Default
7 Latch 6 Hold
Error Mask Register 0x01 (Byte 3) 0x02 0x3F
5 Fast2 4 Fast1 3 ADCOVL 2 BQLO 1 OCOMP 0 GCOMP
GCOMP OCOMP BQLOW ADCOVL FAST1 FAST2 HOLD LATCH
Enable Gain Error Detection Enable Offset Error Detection Enable Sensor Breakage Detection Enable ADC Clipping Detection Enable Speed monitoring (Counter and A/B-Signals) Enable Speed monitoring (A/B-Signals) Deactivate square-wave outputs in event of an error Store error states
For detailed Information about the meaning of the bits refere to chapter 8.
For square wave operation (A/B-Signals) it is recommended to set the error mask register to 0x3F or 0xFF respectively, in counter mode use the error mask register loaded with 0xDF and set the SPEED bit in the CFG0 register.
SYNC Write Address Default
7 ASYNC 6 0
SPI-Synchronization Register 0x03 0x00
5 0 4:0 SYNCVAL
ASYNC
0 1
Import read data with SPI-RD0/ST the next time the contents of the cycle counter and SYNCVAL are identical Import read data always with SPI-RD0/ST Sequential control counter compare value for SPI synchronization
SYNCVAL
For more detailed information about the functions of these bits refer to chapter 5.2.3
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TSTCFG Write Address Default
Configuration IC-Test 0x04 0x00
*)
7:3 2 1:0 00000*) TSTRB 00*) Bits must remain unchanged in order to guarantee the correct functioning of the IC
TSTRB
0 1
Configure pin OREF as index point output Configure pin OREF as Strobe-Signal for the parallel Interface
SGAIN CGAIN Read Address Write Address Default
Gain Correction Value, Sine Gain Correction Value, Cosine 0x04 / 0x05 (Byte 0) 0x07 / 0x09 0x80
7:0 GAIN
GAIN
Current value of the gain correction registers (unsigned, binary) Scaling: 0x00 Factor 0.5 0x80 Factor 1 0xFF Factor 1.5
SOFF COFF Read Address Write Address Default
Offset Correction Value, Sine Offset Correction Value, Cosine 0x04 / 0x05 (Byte 1) 0x08 / 0x0A 0x00
7:0 OFFSET
OFFSET
Current value of the offset correction registers (two's complement) Scaling: 0x80 Maximum Offset negative (-25% ADC Maximum) 0x00 No Offset 0x7F Maximum Offset positive (+25% ADC Maximum)
Write accesses to the SOFF/COFF/SGAIN/CGAIN register serve for pre-setting - these registers are permanently updated by the internal automatic gain-offset-controller. The scaling factor indicated applies to the behaviour of the adjustment register; it does not describe the maximum signal error possible.
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7
Measurement Trigger
A signal edge event on pin TRG/GFE stores the current measurement result (counter value) in one of the two-level deep trigger hold register. The active trigger edge is configured by the configuration bit TRGSLP (register CFG1). A read access to the register MVAL returns the "oldest" value of the trigger hold register. If the trigger register contains no active value, the current counter value returns in result of the read access. It is possible to save the results of two trigger events. While not both trigger register would be read out, all following trigger events are ignored. The TRGOVL bit in register MVAL is set, if a trigger event occurs and both trigger hold register contains valid data. Every SPI read access to the register MVAL releases one trigger hold register. Only if trigger hold register 1 is empty (TR1=0), a new trigger processing is possible. If the parallel interface used solely as output port, the pin CLRTRG must be operated to confirm the reading of one trigger event result. A logic "1" in the FROZEN bit out of the register MVAL indicates the source of the read value as trigger result. A logic "0" in this bit indicates the read access as normal read of the counter value. The actual state of the trigger is coded in the bits TR(1:0)of the status register (STAT). TR(1:0) TRGOVL 00 0 01 0 10 0 11 0 10 1 11 1 FROZEN 0 1 1 1 1 1 MVAL contents Current counter value Trigger Hold Register 0 Trigger Hold Register 1 Trigger Hold Register 0 Trigger Hold Register 1 Trigger Hold Register 0 next Trigger Event Storing to Trigger Hold Register 0 Storing to Trigger Hold Register 1 Storing disabled, TRGOVL will be set Storing disabled, TRGOVL will be set Storing disabled, TRGOVL is set Storing disabled, TRGOVL is set
For applications which need fast response time related to trigger events and a high data rate on the serial port as well , it could be better to read out only the 16 LSB of the MVAL register to check out if a trigger event occurred.
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8
Error Processing
The IP200 has 6 sources for generating the global error signal. Each source can be activated by the corresponding bit in the error mask register. With the LatchErr bit being activated, the individual error signals are stored until the next chip reset or until the next SPI ResetCount command (command 0x01) occurs, respectively. The logic OR function of the masked and stored error signals appears as a low active signal on pin NERR. With the HoldErr bit being active, the A, B and OREF outputs freeze in the current state on error case. The NERR and NRES pins can be shorted in order to re-synchronise the IC in the event of an error. The error signal is active for 8 system clocks in this case. Error Mask Register Bit GCOMP OCOMP BQLOW ADUOVL FAST1 FAST2 HoldErr LatchErr Description (if bit is set) Gain controller reaches his limit Offset controller reaches his limit Amplitude Error: the resulting Sine-Cosine-Vector is to small One or both ADC-Converter are clipping Signal frequency to high, no signal direction recognition possible (SPEED=1), Signal frequency to fast for proper generating A/B/OREF - Signals (SPEED=0) Signal frequency to fast for proper generating the A/B/OREF - Signals (depends upon IT(2:0), refer also to table "Clock Frequency Examples" in chapter 4.4) The A/B/OREF - Signals freeze in error case The masked error signal is stored until next SPI-reset-command or a global reset occurs, respectively
For square wave operation (A/B-Signals) it is recommended to set the error mask register to 0x3F or 0xFF respectively, in counter mode use the error mask register loaded with 0xDF and set the SPEED bit in the CFG0 register. The status register STAT contains all error bits. The MVAL and CNT register contain logic combinations of counter relevant error bits: SENSERR = ADUOVL or BQLOW or OCOMP or GCOMP AMPERR = ADUOVL or BQLOW
Sensor breakage error: Partial or complete tearing off of the connected sensor is detected in the IP200 at the time of occurrence. Thereafter, the automatic gain-offset-controller tries to compensate this error which, due to the large operating range of the gain-offset-controller, can lead to a situation where the cause of this error seems to have been eliminated.
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9
Reset / Configuration
The IP200 IC does not contain an internal Power-On-Reset circuit! It is essential to supply the IP200 with an external reset signal on pin NRES. This reset signal must appear low until 3ms after VDD rising to a voltage level of 4.75V. If NRES and NERR are shorted, the error signal is held through the "NERR -chain" while one of the chain flipflops contains a "0".
Reset (LOW-active) to all Flip Flops in the IC VDD
NRES
internal NERR CLK NRES
D
Q CLK
D
Q
NERR
Chain of Flip Flops, not affected by NRES-Signal
IP200
Figure 13
9.1
Reset Processing 1. 2. 3. 4. 5. Pin SDO/RDY goes to L, all register will be initialised with default values. The IC is operating a self-calibration, the configuration pins are read into the CFG0 register. Start of normal operation. Pin SDO/RDY goes to H (external pull-up required). The configuration register could be changed via SPI interface.
The time between the rising edge of NRES and the rising edge of SDO/RDY, which means the end of the reset process, amount to approximately 1365 system clocks.
9.2
Configuration
There are two different types of configuration possible: Configuration via input pins The register CFG0 will be configured via the input pins IR(2:0), IT(2:1), TRG/GFE and SDI/SPEED. All other registers are initialised with default values. Suitable for low-cost single-chip and standard applications. Configuration via SPI Pins DP(3:0) select SPI hardware address (for multi-channel systems only). Suitable for applications with SPI interface, for example microcontroller systems.
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9.3
Configuration Bits Defaults Description Interpolation Rate Interval Time Interval Time Glitch-Filter-Enable Speed-Mode for internal Counter Disable automatic controller Disable Index Point Trigger Edge Enable Strobe-Signal on pin OREF Error Mask Register Initial value Gain Correction, Sine Initial value Offset Correction, Sine Initial value Gain Correction, Cosine Initial value Offset Correction, Cosine SPI synchronisation with internal sequential control counter Default Pin IR(2:0)is read Pin IT(2:1)is read 0 Pin TRG/GFE is read Pin SDI/SPEED is read 0 0 0 0 0x3F 0x80 0x00 0x80 0x00 0x00
Name IR(2:0) IT(2:1) IT(0) GFE SPEED DISREG DISREF TRSLP TSTSTRB ERRMASK SGAIN SOFF CGAIN COFF SYNC
10 Signal Propagation Time
The delay time between the sampling point of the analogue input signals (sine/cosine) and the availability of the interpolation result (i.e. related to trigger) totals 90 system clocks. The delay time between sampling and updating the data registers and those values available via parallel or serial interface, respectively, totals 96 system clocks. If a external counter unit connected to the A/B/OREF outputs is used, the time between sampling and output of resulting square waves totals 122 system clocks. Every 32nd system clock a new measurement result appears on the parallel data output. Note that the data transferring time of the used interface is added to the IP200 internal system propagation time.
Sample s(t) ADC-Data Trigger Event Result DATA Register SPI / Parallel ext. counter unit con. to A/B
N
Index Point N+1 N+2 N-1 N N-2 N-2 N+1 N-1 N-1 N N N+3 N+2 N+4 N+3 N+1 N+1 N+5 N+4 N+2 N+2
N+6
N-3 N-3
X(N-4)
X(N-3)
X(N-2)
X(N-1)
X(N)
X(N+1)
X(N+2) Index Point: OREF is H
X(N-1) 32x SYSCLK 26x SYSCLK A B X(N-1)-1
X(N-1)+2
X(N-1)+1
X(N-1)+3
Figure 14
Note that the constant delay time of the IC (as with any other digital signal processing systems) result in a frequency-dependent phase shift between the analogue input signals and the output signals (d = 2*f*tv).
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11 Electrical Characteristics
Absolute maximum ratings Min. TYP Max Unit Power supply VDD 0.3 7 V *) Temperature -55 125 C storage temperature -55 155 C ESD 1 kV *) with defined circuit Crossing these ratings can damage the IC; events of maximum supply voltage and maximum temperature at the same time have been to avoid. Recommended Operating Conditions MIN NOM MAX Unit Supply voltages (VDD, VDDA) with respect to Ground (VSS) 4.75 5.0 5.25 V Supply current analogue (@20C) 10 20 35 mA Supply current digital (@20MHz & 20C) 40 mA System clock pulse duration time Low / High 12.5*) 500 ns System clock frequency range fo sc 1 40*) MHz Operating case temperature -20 85 C Digital input and output voltage V_IL 0 0.3 x VDD V Digital input and output voltage V_IH 0.7 x VDD VDD V Digital input and output voltage V_OL***) 0 0.8 V Digital input and output voltage V_OH***) 2 VDD V Crystal**) connected to XA and XB: Internal load capacitance ( XA, XB) 6 pF Power-On-Time 3 ms *) Note that the system clock pulse duration time does not remain under minimum throughout the entire temperature range, if a crystal is used. **) The IP200 circuit is intended for series resonant fundamental mode operation. ***) I_out max. 4mA Interpolation Input frequency range Automatic gain control range Automatic offset control range Interpolation Rates Minimum interval time A/B - Signals Interpolation accuracy @ I-Rate = 200, f< 100kHz Interpolation accuracy @ I-Rate = 200, 250kHz related to nom. amplitude
20% 10% 20 / 25 / 40 / 50 / 80 / 100 / 160 / 200 1 / fosz 128 / fo sz 0.7 1.2 2 90 / fosc 122 / fo sc 0 fosc / 32 4 / fosc + 15 2048/ fosc NOM MAX VDD-1.2 <1 400 0.5 1.2 VCC - 1.5V
ns Inc. Inc. ns ns MHz ns ns Unit V A kHz Vpp V dB dB nF F A mV mV
Analogue Input Specifications MIN Input voltage range analog pins* ) 0 Input current analog pins*) Input impedance analog pins*) Input frequency range SIINP,SINN,COSP,COSN (< 1dB attenuation) Phase offset between SIN and COS @100kHz Peak to peak input voltage SINN SINP / COSN COSP 0.8 Common Mode Level SINN SINP / COSN COSP 1.5 CMRR (< 5Hz) 66 PSRR (< 5Hz) 66 Input Impedance Load capacitance at OUTS/OUTC @ RS = 510 Load capacitance at OUTS/OUTC @ RS > 2k Source current at V0 -100 Phase deviation 10.5 Switching voltage of index point comparator -6 Hysteresis of index point comparator 8 *) at the pins SINP, SINN, COSP, COSN, REFP, REFN, INPS and INPC
6pF||1G
1.0 VCC / 2
1G||8pF 1 10 100 12 6 20
11.3 0 12
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ADC Input Impedance Mid voltage usable for external circuits positive Reference voltage sine-ADC RSH positive Reference voltage cosine-ADC RCH negative Reference voltage sine-ADC RSL negative Reference voltage cosine-ADC RCL Signal amplitude in case of direct connection to the ADC
MIN 2.325 3.22 3.22 1.39 1.39
NOM 100M||20pF 2.375 3.3 3.3 1.45 1.45 2.4
MAX 2.425 3.42 3.42 1.53 1.53
Unit V V V V V VPP
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12 Mechanical Characteristics
12.1 Pinout
Pin Name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DATA(0) DATA(1) DATA(2) DATA(3) DATA(4) DATA(5) DATA(6) DATA(7) DATA(8) DATA(9) DATA(10) DATA(11) DATA(12) DATA(13) DATA(14) DATA(15) VSS2 VDD2 OUTHIGH CLRTRG XB XA SCLK SCEN
SDI / SPEED
Type
COUT COUT COUT COUT COUT COUT COUT COUT COUT COUT COUT COUT COUT COUT COUT COUT DSUP DSUP COUT TTLIN OSC OSC TTLIN TTLIN TTLIN CODO DSUP TTLIN ASUP ASUP AIN AIN
Description
Data Output Port Data Output Port Data Output Port Data Output Port Data Output Port Data Output Port Data Output Port Data Output Port Data Output Port Data Output Port Data Output Port Data Output Port Data Output Port Data Output Port Data Output Port Data Output Port Digital Ground Digital Supply MSB at Parallel Data Port active Clear Trigger 1) Crystal Input B 1) Crystal Input B / ext. Clock SPI Clock 3) SPI Enable 2) SPI Data Input/ SPEED (Cfg) 1) SPI Data Output 4) Digital Supply Test Mode Input 1) Analogue Ground Analogue Supply Negative Reference Input 6) Positive Reference Input 6)
Pin Name
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 SINP SINN OUTS180 OUTS INPS RSH RSL V0 VSSA2 VDDA2 RCL RCH INPC OUTC COSN COSP PH VDDA3 VSSA3 IT2 IT1 / DP3 IR2 / DP2 IR1 / DP1 IR0 / DP0 OREF B A TRG/GFE NERR NRES VDD1 VSS1
Type
AIN AIN AOUT AOUT AIN AIO AIO AIO ASUP ASUP AIO AIO AIN AOUT AIN AIN AIN ASUP ASUP TTLIN TTLIN TTLIN TTLIN TTLIN COUT COUT COUT TTLIN ODPU TTLIN DSUP DSUP
Description
Positive Signal Input Sine Negative Signal Input Sine 5) Sine Analogue Output (Phase rev.) Sine Analogue Output ADC Input Sine Pos. Reference Voltage SADC Neg. Reference Voltage SADC Analogue Midscale Voltage Analogue Ground Analogue Supply Neg. Reference Voltage CADC Pos. Reference Voltage CADC ADC Input Cosine Cosine Analogue Output Negative Signal Input Cosine 5) Positive Signal Input Cosine Analogue Phase Correction Input 5) Analogue Supply Analogue Ground Interval Time Select 3 3) IT Select 1 / DProg 3 3) Interpolation Rate / DProg 2 3) Interpolation Rate / DProg 1 3) Interpolation Rate / DProg 0 3) Index Point Output Signal Square Wave Output B Square Wave Output A Trigger / Glitch-Filter-Enable 3) Error Output Reset Digital Supply Digital Ground Oscillator - I/O, 6pF Analogue-IO Digital Power Supply Analogue Power Supply
SDO/RDY VDD3 TM VSSA1 VDDA1 REFN REFP
COUT CODO ODPU ODPD TTLIN
1) 2)
CMOS - OUT 4mA CMOS - OUT 4mA / Open-Drain CMOS - OUT 4mA / Open-Drain /w Pull Up CMOS - OUT 4mA / Open-Drain /w Pull Down Input, TTL - Level
OSC AIN / AOUT / AIO DSUP ASUP
if unused, pull Low if unused, pull High 3) if unused, pull Low or High 4) if unused, connect to separate pull up resistor 5) if unused connect to V0 6) if unused, pull the REFP and REFN inputs to different analogue voltage levels. The absolute voltage difference between these pins must exceed the maximum reference comparator input hysteresis range for a comparator safety behaviour
Each IC input pin requires a defined connection!
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12.2 Double Function Pins During reset process (the time between rising edge at NRES input and rising edge at SDO/RDY output) the following pins are required for IC configuration: Name IT1 / IR2 / IR1 / IR0 / TRG / SDI / During Reset Interval Time Interpolation Rate Interpolation Rate Interpolation Rate Glitch Filter Enable SPEED Mode Select After Reset SPI Hardware Address SPI Hardware Address SPI Hardware Address SPI Hardware Address Trigger Signal SPI Data Input
DP3 DP2 DP1 DP0 GFE SPEED
(Initial (Initial (Initial (Initial
value) value) value) value)
The attachment circuit of these pins depends upon the used interface type for measurement result output and the preferred method of configuration. Refer also to the application notes in the document " 4300x-AN-30-E-IPx.pdf".
12.3 Packaging TQFP64 Package:
Figure 15
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43500-DB-2-1-E-IP200.pdf
12.4 Bond Pattern
DATA15 DATA14 563,75 ; 4474 742,75 ; 4474 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 921,75 ; 4474 1100,75 ; 4474 1279,75 ; 4474 1458,75 ; 4474 1637,75 ; 4474 1816,75 ; 4474 1995,75 ; 4474 2174,75 ; 4474 2353,75 ; 4474 2532,75 ; 4474 2711,75 ; 4474 2890,75 ; 4474 3069,75 ; 4474 3248,75 ; 4474
upper right corner x 3915 ; y 4665
VSS2 VDD2 OUTHIGH CLRTRG XB XA SCLK SCEN SDI SDO
57 ; 4099,25 57 ; 3902,80 57 ; 3681,75 57 ; 3472,10 57 ; 3214,70 57 ; 3056,70 57 ; 2780,70 57 ; 2555,10 57 ; 2342,15 57 ; 2164,80
3724 ; 4101,75 VSS1 3724 ; 3894,30 VDD1
Digital Circuit
3724 ; 3671,10 NRES 3724 ; 3457,00 NERR 3724 ; 3246,90 TRG 3724 ; 3015,90 A 3724 ; 2819,30 B
IP200
ADC ADC
3724 ; 2634,20 OREF 3724 ; 2376,10 IR0 3724 ; 2198,60 IR1 3723 ; 1785,75 IR2 3723 ; 1581,05 IT1 3723 ; 1376,35 IT2 3723 ; 1166,05 V0C 3723 ; 991,25 VSSA3 3723 ; 830,00 VDDA3 3723 ; 590,50 V0S180 3723 ; 339,85 PH
VSSZ 58 ; 1798,20 VDD3 58 ; 1639,80 TM 58 ; 1382,30
VSSA1 58 ; 1162,85 VDDA1 58 ; 988,85 REFN 58 ; 758,50 REFP 58 ; 571,65 V0S 58 ; 345,40
Analog Circuit
719,75 ; 58
x -35; y -35 lower left corner
OUTS180
x
Notes: 1. All linear dimensions are in m. 2. All pad dimensions refer to metall layer 2. 3. Pad size: 99,000 x 99,000. 4. Pad center point: X+49,500 x Y+49,500. 5. Dimension of lower left corner of bond window refer to pad dimensions: X+7,000 x Y+7,000. 6. Size of bond window: 85,000 x 85,000.
GEMAC
Gesellschaft fur Mikroe lektronikanwendung Chemnitz mbH
Zwickauer Strae 227 D-09116 Chemnitz, Germany
+49 371 33 77 - 0 +49 371 33 77 272 www.gemac-chemnitz.de interpolation@gemac-chemnitz.de sales@gemac-chemnitz.de Date: 20.04.04 Page 28 of 30 Phone: Fax:: Internet: Email:
OUTS
SINP
SINN
y
VSSA2 2026,00 ; 58 VDDA2 2199,60 ; 58
COSN 3264,55 ; 58
Title:
Data Sheet GC-IP200
Name of Document:
43500-DB-2-1-E-IP200.pdf
COSP 3484,55 ; 58
RSH 1379,75 ; 58
OUTC 3044,55 ; 58
INPS 1159,75 ; 58
RCL 2393,15 ; 58
INPC 2824,55 ; 58
939,75 ; 58
RCH 2622,40 ; 58
RSL 1599,75 ; 58
V0 1819,75 ; 58
279,75 ; 58
499,75 ; 58
Pin Name TQFP64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 VSS2 VDD2 OUTHIGH CLRTRG XB XA SCLK SCEN SDI SDO VDD3 TM VSSA1 VDDA1 REFN REFP SINP SINN OUTS180 OUTS INPS RSH RSL V0 VSSA2 VDDA2 RCL RCH INPC OUTC COSN COSP PH VDDA3 VSSA3
Pads, lower left corner Metal 2 (99 x 99) Bond (85 x 85) Centre Point x y x y x y 3248,75 4474,00 3255,75 4481,00 3298,25 3069,75 4474,00 3076,75 4481,00 3119,25 2890,75 4474,00 2897,75 4481,00 2940,25 2711,75 4474,00 2718,75 4481,00 2761,25 2532,75 4474,00 2539,75 4481,00 2582,25 2353,75 4474,00 2360,75 4481,00 2403,25 2174,75 4474,00 2181,00 4481,00 2224,25 1995,75 4474,00 2002,75 4481,00 2045,25 1816,75 4474,00 1823,75 4481,00 1866,25 1637,75 4474,00 1644,75 4481,00 1687,25 1458,75 4474,00 1465,75 4481,00 1508,25 1279,75 4474,00 1286,75 4481,00 1329,25 1100,75 4474,00 1167,75 4481,00 1150,25 921,75 4474,00 928,75 4481,00 971,25 742,75 4474,00 749,75 4481,00 792,25 563,75 4474,00 570,75 4481,00 613,25 57,00 4099,25 64,00 4106,25 106,50 57,00 3902,80 64,00 3909,80 106,50 57,00 3681,75 64,00 3688,80 106,50 57,00 3472,10 64,00 3479,10 106,50 57,00 3214,70 64,00 3221,70 106,50 57,00 3056,70 64,00 3063,70 106,50 57,00 2780,70 64,00 2787,70 106,50 57,00 2555,10 64,00 2562,10 106,50 57,00 2342,15 64,00 2349,15 106,50 57,00 2164,80 64,00 2171,80 106,50 58,00 1639,80 65,00 1646,80 107,50 58,00 1382,30 65,00 1389,30 107,50 58,00 1162,85 65,00 1169,85 107,50 58,00 988,85 65,00 995,85 107,50 58,00 785,50 65,00 792,50 107,50 58,00 571,65 65,00 578,65 107,50 279,75 58,00 286,75 65,00 329,25 499,75 58,00 506,75 65,00 549,25 719,75 58,00 726,75 65,00 769,25 939,75 58,00 946,75 65,00 989,25 1159,75 58,00 1166,75 65,00 1209,25 1379,75 58,00 1386,75 65,00 1429,25 1599,75 58,00 1606,60 65,00 1649,25 1819,75 58,00 1826,75 65,00 1869,25 2026,00 58,00 2033,00 65,00 2075,50 2199,60 58,00 2206,60 65,00 2249,10 2393,15 58,00 2400,15 65,00 2442,65 2622,40 58,00 2629,40 65,00 2671,90 2824,55 58,00 2831,55 65,00 2874,05 3044,55 58,00 3051,55 65,00 3094,05 3264,55 58,00 3271,55 65,00 3314,05 3484,55 58,00 3491,55 65,00 3534,05 3723,00 339,85 3730,00 346,85 3772,50 3723,00 830,00 3730,00 837,00 3772,50 3723,00 991,25 3730,00 998,25 3772,50
4523,50 4523,50 4523,50 4523,50 4523,50 4523,50 4523,50 4523,50 4523,50 4523,50 4523,50 4523,50 4523,50 4523,50 4523,50 4523,50 4148,75 3952,30 3731,25 3521,60 3264,20 3106,20 2830,20 2604,60 2391,65 2214,30 1689,30 1431,80 1212,35 1038,35 835,00 621,15 107,50 107,50 107,50 107,50 107,50 107,50 107,50 107,50 107,50 107,50 107,50 107,50 107,50 107,50 107,50 107,50 389,35 879,50 1040,75
GEMAC
Gesellschaft fur Mikroe lektronikanwendung Chemnitz mbH
Zwickauer Strae 227 D-09116 Chemnitz, Germany
+49 371 33 77 - 0 +49 371 33 77 272 www.gemac-chemnitz.de interpolation@gemac-chemnitz.de sales@gemac-chemnitz.de Date: 20.04.04 Page 29 of 30 Phone: Fax:: Internet: Email:
Title:
Data Sheet GC-IP200
Name of Document:
43500-DB-2-1-E-IP200.pdf
Pin Name TQFP64 52 53 54 55 56 57 58 59 60 61 62 63 64 IT2 IT1 IR2 IR1 IR0 OREF B A TRG NERR NRES VDD1 VSS1
Pads, lower left corner Metal 2 (99 x 99) Bond (85 x 85) Centre Point x y x y x y 3723,00 1376,35 3730,00 1383,35 3772,50 3723,00 1581,05 3730,00 1588,05 3772,50 3723,00 1785,75 3730,00 1792,75 3772,50 3724,00 2198,60 3731,00 2265,60 3773,50 3724,00 2376,10 3731,00 2383,10 3773,50 3724,00 2634,20 3731,00 2641,20 3773,50 3724,00 2819,30 3731,00 2826,30 3773,50 3724,00 3015,90 3731,00 3022,90 3773,50 3724,00 3246,90 3731,00 3253,90 3773,50 3724,00 3457,00 3731,00 3464,00 3773,50 3724,00 3671,00 3731,00 3678,60 3773,50 3724,00 3894,30 3731,00 3901,30 3773,50 3724,00 4101,75 3731,00 4108,75 3773,50
1425,85 1630,55 1835,25 2248,10 2425,60 2683,70 2868,80 3065,40 3296,40 3506,50 3720,50 3943,80 4151,25
13 Revision History
Date 16.04.02 16.05.02 07.01.04 20.04.04 No. 1.0 1.1 2.0 2.1 Modification First preparation Modification page 10 Diverse modifications and additions SPI protocol corrections, supplementation of mechanical and electrical parameters Status preliminary preliminary actual actual
GEMAC
Gesellschaft fur Mikroe lektronikanwendung Chemnitz mbH
Zwickauer Strae 227 D-09116 Chemnitz, Germany
+49 371 33 77 - 0 +49 371 33 77 272 www.gemac-chemnitz.de interpolation@gemac-chemnitz.de sales@gemac-chemnitz.de Date: 20.04.04 Page 30 of 30 Phone: Fax:: Internet: Email:
Title:
Data Sheet GC-IP200
Name of Document:
43500-DB-2-1-E-IP200.pdf

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